(1) Field of the Invention
This invention relates to a semiconductor memory, and more particularly, to a semiconductor memory having ferroelectric memory cells.
(2) Description of the Related Art
A flash memory and a ferroelectric memory are known as nonvolatile memories which can store information after power is turned off.
A flash memory has a floating gate embedded in a gate insulating film of an insulated gate field-effect transistor (IGFET) and stores information by accumulating electric charges indicative of the information in this floating gate. With a flash memory, however, a tunnel current must be passed through a gate insulating film to write or erase information. Accordingly, a comparatively high voltage must be applied.
On the other hand, a ferroelectric memory is also known as a ferroelectric random access memory (FeRAM) and stores information by making use of the hysteresis characteristic of a ferroelectric film included in a ferroelectric capacitor. This ferroelectric film polarizes according to voltage applied between an upper electrode and a lower electrode of the capacitor. Even after the voltage is removed, spontaneous polarization remains. When the polarity of the applied voltage is reversed, the direction of the spontaneous polarization is also reversed. Therefore, by associating the directions of the spontaneous polarization with “1” and “0,” information is written to the ferroelectric film. Voltage necessary for this writing is lower than voltage applied to a flash memory. In addition, high-speed writing can be performed compared with a flash memory.
In order to reduce the power consumption of a ferroelectric memory including memory cells each having such a ferroelectric capacitor, the following memory cell array in which word lines are arranged like stairs is disclosed (see, for example, Japanese Unexamined Patent Publication No. 2001-358312).
FIG. 7 shows an example of a memory cell array included in a conventional ferroelectric memory.
A memory cell array 800 includes a plurality of memory cells arranged in a matrix form, bit lines BL1, BL2, BL3, and BL4 and complementary bit lines /BL1, /BL2, /BL3, and /BL4 arranged in a column direction, and word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8, WL9, WL10, and WL11 and capacitor plate lines PL1, PL2, PL3, PL4, PL5, PL6, PL7, PL8, PL9, PL10, and PL11 arranged in a row direction. The word lines WL1 through WL11 are arranged like stairs so that each of them will connect with ferroelectric memory cells in different rows in the column direction.
Each memory cell includes, for example, two metal oxide semiconductor (MOS) transistors and two ferroelectric capacitors and is what is called a 2T2C cell. For example, a memory cell 801 includes MOS transistors 801a and 801b and ferroelectric capacitors 801c and 801d. One input-output terminal of the MOS transistor 801a is connected to the bit line BL4 and one input-output terminal of the MOS transistor 801b is connected to the complementary bit line /BL4. The other input-output terminal of the MOS transistor 801a is connected to one terminal of the ferroelectric capacitor 801c and the other input-output terminal of the MOS transistor 801b is connected to one terminal of the ferroelectric capacitor 801d. Gates of the MOS transistors 801a and 801b are connected to the word line WL1. The other terminal of the ferroelectric capacitor 801c and the other terminal of the ferroelectric capacitor 801d are connected to the capacitor plate line PL4.
An area in the memory cell array 800 including (8×4) memory cells from the bottom is a real memory area 810 really used for memory access. An area above the real memory area 810 is a dummy area 811. The structure of a memory cell array in the dummy area 811 is the same as that of a memory cell array in the real memory area 810. However, the dummy area 811 is not used for memory access but used for arranging the word lines WL1, WL2, and WL3 which connect with memory cells in the real memory area 810.
It is assumed that the memory cell 801 located at the row address “0111” and the column address “11” is selected from the memory cell array 800 having the above structure.
To select the memory cell 801, the capacitor plate line PL4 located at the row address “0111” is driven by a capacitor plate line drive circuit (not shown). To select one of the word lines WL1 through WL11 to be driven, the following conversion must be made because the word lines WL1 through WL11 are arranged like stairs.
To select the memory cell 801 located at the row address “0111” and the column address “11,” an adder (not shown) adds these addresses together. “0111”+“11”=“1010,” so a word line drive circuit (not shown) drives the word line WL1 located at the row address “1010”. As a result, the memory cell 801 is selected.
When the word line WL1 is driven, the MOS transistors 801a and 801b included in the memory cell 801 go into the ON state. When data is written, voltage is applied between the bit line BL4 or the complementary bit line /BL4 and the capacitor plate line PL4. By doing so, the predetermined data (polarization direction) is written to the ferroelectric capacitors 801c and 801d. The memory cell 801 is a 2T2C cell. Therefore, if “1” is stored in the ferroelectric capacitor 801c, then “00” is stored in the ferroelectric capacitor 801d. The word line WL1 is driven again at read time. The MOS transistors 801a and 801b go into the ON state. The data is read out by amplifying the difference in potential between the bit line BL4 and the complementary bit line /BL4 electrically connected to the ferroelectric capacitors 801c and 801d respectively with a sense amplifier (not shown).
With the memory cell array 800 having the above structure, the number of ferroelectric memory cells simultaneously selected is one when the capacitor plate line PL4 and the word line WL1, for example, are activated. Therefore, power consumption can be reduced and high-speed operation can be realized.
FIG. 8 is a schematic view showing the structure of a conventional semiconductor memory having ferroelectric memory cells.
In FIG. 8, each black dot indicates a memory cell 901. A word line WL connected to the memory cell 901 is actually arranged like stairs. This is the same with the word lines WL1 through WL11 shown in FIG. 7. In FIG. 8, however, the word line WL is simplified by using a slant line. Bit lines (including complementary bit lines) are not shown.
A semiconductor memory 900 has a memory cell array including a real memory area 902a and a dummy area 903a and a memory cell array including a real memory area 902b and a dummy area 903b. Memory cells are not shown in the dummy areas 903a and 903b. 
WL/PL drive circuit sections 904-1, . . . , 904-n, 904-(n+1), . . . , 904-m for driving word lines WL and capacitor plate lines PL are arranged between the two memory cell arrays.
The WL/PL drive circuit sections 904-1 through 904-n drive capacitor plate lines PLr and word lines WL in the real memory areas 902a and 902b. The WL/PL drive circuit sections 904-(n+1) through 904-m drive word lines WL for selecting part of the memory cells in the real memory areas 902a and 902b. The WL/PL drive circuit sections 904-(n+1) through 904-m are connected to capacitor plate lines PLd in the dummy areas 903a and 903b, but the WL/PL drive circuit sections 904-(n+1) through 904-m are not used for driving the capacitor plate lines PLd. Accordingly, the memory cells in the dummy areas 903a and 903b cannot be selected.
The semiconductor memory 900 also has a peripheral circuit section 905 including a sense amplifier, an adder, a column selection circuit, a timing generation circuit, and a decoder for selecting a word line WL or a capacitor plate line PLr to be driven and pad sections 906 and 907 for inputting various kinds of voltages and outputting a signal read out from a memory cell 901.
Each of the WL/PL drive circuit sections 904-1 through 904-m includes a word line drive circuit and a capacitor plate line drive circuit. The structure of the word line drive circuit is approximately the same as that of the capacitor plate line drive circuit. The structure of an example of a word line drive circuit 910 will now be described.
FIG. 9 is a circuit diagram of an example of a conventional word line drive circuit.
The word line drive circuit 910 includes NAND circuits 911, 912, and 913, inverter circuits 914, 915, and 916, p-channel MOS transistors (PMOSes) 917 and 918, n-channel MOS transistors (NMOSes) 919 and 920, and ferroelectric capacitors 921 and 922.
One input terminal of the NAND circuit 911 is connected to a step-up terminal BST1. One input terminal of the NAND circuit 912 is connected to a step-up terminal BST2. One input terminal of the NAND circuit 913 is connected to a step-up terminal BST3. The respective other input terminals of the NAND circuits 911, 912, and 913 are connected to a decode terminal DEC.
An output terminal of the NAND circuit 911 is connected to gates of the NMOSes 919 and 920 and is connected to a gate of the PMOS 917 via the inverter circuit 914. An output terminal of the NAND circuit 912 is connected to one terminal of the ferroelectric capacitor 921 via the inverter circuit 915. An output terminal of the NAND circuit 913 is connected to one terminal of the ferroelectric capacitor 922 via the inverter circuit 916.
Power supply voltage VDD is applied to one input-output terminal of the PMOS 917. The other input-output terminal of the PMOS 917 is connected to one input-output terminal of the NMOS 919, the other terminal of the ferroelectric capacitor 921, and a gate of the PMOS 918. The other input-output terminal of the NMOS 919 is grounded.
The power supply voltage VDD is applied to one input-output terminal of the PMOS 918. The other input-output terminal of the PMOS 918 is connected to one input-output terminal of the NMOS 920, the other terminal of the ferroelectric capacitor 922, and an output terminal OUT. The other input-output terminal of the NMOS 920 is grounded. The output terminal OUT is connected to a word line WL shown in FIG. 8. That is to say, the number of the word line drive circuits 910 located is equal to that of the word lines WL included in the memory cell arrays.
The operation of the word line drive circuit 910 will now be described in brief.
The adder included in the peripheral circuit section 905 performs an addition process in the above-mentioned way by using addresses of a memory cell selected to specify which word line WL to select. When the word line WL to be driven by the word line drive circuit 910 is selected, the decode terminal DEC of the word line drive circuit 910 changes to the high (H) level. At this time the step-up terminals BST1, BST2, and BST3 are changed to the H level in that order by the timing generation circuit included in the peripheral circuit section 905. Then, three-stage step-up operation is performed by electric charges stored in the ferroelectric capacitors 921 and 922 and the word line WL is driven.
The structure of the capacitor plate line drive circuit is approximately the same as that of the word line drive circuit 910.
As shown in FIG. 8, however, the conventional semiconductor memory using the word lines arranged like stairs includes the dummy areas 903a and 903b where a memory cell cannot be selected. In addition, the dummy areas 903a and 903b have the shape of a triangle and blank areas opposite the dummy areas 903a and 903b also have the shape of a triangle. Accordingly, it is difficult to locate other circuits in these blank areas. As a result, there is a strong possibility that these blank areas really become dead space.
Furthermore, the WL/PL drive circuit sections 904-(n+1) through 904-m which can drive word lines and capacitor plate lines are located in the areas where only word lines are driven, which causes the increase in the area of a chip.